This invention relates to programmable logic array integrated circuit devices, and more particularly to programmable logic array integrated circuit devices in which some portions of the device are provided with substantially more interconnection resources than other portions of the device are provided with.
A typical programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each region is programmable to perform any one or more of several logic functions on plural input signals applied to that region. Each region produces one or more output signals indicative of the results of the logic function(s) performed by that region. Programmable interconnection resources are provided on the device for such purposes as bringing input signals to each logic region and conveying output signals from the logic regions. These interconnection resources also bring input signals into the logic of the device from external circuitry and convey output signals from the logic of the device to that external circuitry. The interconnection resources include programmable switches for allowing many different signal routings throughout the device.
The above-described devices are typically intended as general-purpose devices. Thus the designer of a device does not know all the uses to which purchasers ("users") of the device may want to put it. Despite this lack of specific knowledge, however, the designer's objective is generally to provide a design which will satisfy the greatest number of reasonably possible uses. This typically means supplying both the largest amount of logic, and also supplying sufficient interconnection resources so that any desired interconnections can be made without other necessary interconnections being blocked or the interconnection resources being exhausted. These two objectives are somewhat conflicting, of course, because space on the device that is devoted to interconnection resources is not available for logic and vice versa. Also, as the amount of logic increases, the number of possible interconnections tends to increase at least geometrically and perhaps exponentially. On the other hand, most uses of the device will not require use of anywhere near all of the theoretically possible interconnections. Providing completely general interconnection resources would also tend to unduly load the circuitry, thereby increasing the power required to drive it and/or slowing it down. Thus, for reasons of practicality, economy, speed, etc., the designer is obliged to select from completely general interconnection resources a subset of those resources which will be sufficient in the largest reasonably possible number of probable uses of the device without providing substantially more than that amount of such resources. This is an extremely difficult aspect of device design, and many different approaches have been taken to it.
The present inventor has observed that although prior art programmable logic array integrated circuit devices tend to have interconnection resources that are distributed substantially uniformly throughout the device, most uses of the device involve some logic portions that require substantially more interconnection resources than other logic portions.
In view of the foregoing, it is an object of this invention to provide programmable logic array integrated circuit devices with available interconnection resources that more closely match the requirements for such resources of the typical user logic those devices are used to implement.
It is a more particular object of this invention to provide programmable logic array integrated circuit devices with interconnection resources that are more efficiently distributed, for example, to better match the typical distribution of the need for such resources in the user logic typically implemented by those devices.